In systems where the counter may overflow or underflow, since no interrupt requests are generated, the
user must ensure that the CPU reads the counter periodically. Maximum period is $8000 counts at maximum
signal frequency. Two's complement arithmetic can then be used by the CPU to maintain position
and direction information.
When initialized, the function is configured so that the first edge on either channel results in a counter
update. In order to distinguish between the two channels, this note uses the convention of referring to
the channel with the lower channel number as the primary channel. The other channel is referred to as
the secondary channel.
2.2 Discrete Input/Transition Counter
3 Function Code Size
21 μ instructions + 8 entries = 29 long words
4 Function Parameters
A single channel programmed to run QDEC can be used as a digital input pin with a transition counter.
Total TPU function code size determines what combination of functions can fit into a given ROM or em-ulation
memory microcode space. QDEC function code size is:
This section provides detailed descriptions of function parameters stored in channel parameter RAM.
Figure 3
shows TPU parameter RAM address mapping.
Figure 4 shows the parameter RAM assignment
used by the function. In the diagrams, Y = M111, where M is
the value of the module mapping bit
(MM) in the system integration module configuration register (Y = $7 or $F).
Figure 3 TPU Channel Parameter RAM CPU Address Map
Figure 4 Function Parameter RAM Assignment
During initialization of the function.
During the service of a TCR1 read host service request issued by the host CPU.
This parameter can be used along with EDGE_TIME to perform position and speed interpolation at slow
count rates. TCR1_VALUE can reside in the parameter RAM of either or both QDEC channels, but the
parameter is only updated for the channel that receives the host service request from the CPU. Since
the TPU must respond to the HSR before copying the TCR1 value to parameter RAM, the value ob-tained
does not exactly correspond to the TCR1 value at the time the HSR is issued. The difference
depends on the latency of the TPU and the prescaler value of TCR1. See 7 Performance and Use of
Function
for details.
4.2 CHAN_PINSTATE
The CHAN_PINSTATE parameters are also used to determine the phase (lead/ lag) relationship be-tween
The CPU must not write CHAN_PINSTATE parameters while QDEC is running, or an erroneous update
4.3 CORR_PINSTATE_ADDR
4.4 EDGE_TIME_LSB_ADDR
4.5 EDGE_TIME
EDGE_TIME can reside in the parameter RAM of either QDEC channel, but because both parameters
4.6 POSITION_COUNT
POSITION_COUNT can reside in the parameter RAM of either QDEC channel, but because both pa-rameters
4.7 HSQ0
5 Host Interface to Function
These 16-bit parameters (one for each channel) are maintained by the TPU. Each parameter contains
a value that represents the logic level of the channel pin when the last valid transition was serviced. The
value $8000 is used to represent a pin high level, and $0000 to represent a pin low level. When an edge
is serviced, the new pin state is compared with the last pin state stored in CHAN_PINSTATE Ñ if the
states are the same, then a valid transition has not occurred (noise) and the counter is not updated.
the two QDEC channels so that POSITION_COUNT is updated in the correct direction. To per-form
this lead/ lag test, the channel compares its new pin state with the CHAN_PINSTATE parameter
of the other QDEC channel (obtained via CORR_PINSTATE_ADDR) and from the relationship takes
the appropriate action. See 9 Function Algorithm
for an explanation of the lead/ lag tests.
of POSITION_COUNT can occur.
These parameters (one for each channel) are initialized by the CPU to contain the address in parameter
RAM of the CHAN_PINSTATE parameter of the corresponding QDEC channel. They are used to obtain
the CHAN_PINSTATE parameter of the corresponding channel for the lead/ lag test. For example, if
channels 0 and 1 are being used for QDEC, the CORR_PINSTATE_ADDR of channel 0 should be $16
and CORR_PINSTATE_ADDR of channel 1 should be $06. These parameters are written once prior to
initialization and must not be changed while QDEC is running.
These parameters (one for each channel) are initialized by the CPU to contain the address in parameter
RAM of the LSB (odd address) of the EDGE_TIME parameter. The EDGE_TIME_LSB_ADDR param-eters
of both QDEC channels must point to the same parameter RAM location for the QDEC function
to operate correctly. This parameter is used to access both EDGE_TIME and POSITION_COUNT pa-rameters.
For example, if channels 0 and 1 are being used for QDEC and EDGE_TIME and
POSITION_COUNT are chosen to reside in channel 1, then the EDGE_TIME_LSB_ADDR of both
channels 0 and 1 must be programmed to $11. These parameters are written once prior to initialization
and must not be changed while QDEC is running.
This 16-bit parameter, which resides in the parameter RAM of only one QDEC channel, is updated by
the TPU when a valid signal transition is serviced on either channel. It contains the TCR1 value that was
captured in hardware at the time of the signal transition Ñ it thus provides a time stamp for the host
CPU.
are referenced by the EDGE_TIME_LSB_ADDR address pointer, EDGE_TIME must be in the same
parameter RAM as POSITION_COUNT. See 7 Performance and Use of Function
for more details.
This 16-bit counter is the primary output of the QDEC function. POSITION_COUNT resides in the pa-rameter
RAM of only one QDEC channel. POSITION_COUNT can be read or written at any time by the
CPU. Normally, POSITION_COUNT is initialized by the CPU, then left to run as a free running counter.
are referenced by the EDGE_TIME_LSB_ADDR address pointer, POSITION_COUNT must
be in the same parameter RAM as EDGE_TIME.
Host sequence bit 0 is written by the CPU. HSQ0 is used by the TPU to determine whether the channel
being serviced is the primary or secondary channel. HSQ0 of the primary channel must be cleared and
HSQ0 of the secondary channel must be set. The primary channel is normally the channel with the lower
channel number of the pair.
This section provides information concerning the TPU host interface to the QDEC function. Figure 5
is
a TPU address map. Detailed TPU register diagrams follow the figure. In Figure 5
and in the register diagrams, Y = M111, where M is the value of the module mapping bit (MM) in the
system integration module configuration register (Y = $7 or $F).
Figure 5 TPU Address Map
1. Disables the channels by clearing the two channel priority bits on each of the QDEC channels
(not necessary from reset).
2. Selects the QDEC function on both channels by writing the QDEC function number to their func-tion
select bits.
3. Initializes CORR_PINSTATE_ADDR and EDGE_TIME_LSB_ADDR in parameter RAM of both
channels.
4. Initializes POSITION_COUNT to the desired start value.
5. Selects one channel as the primary channel and the other as the secondary channel via HSQ0.
6. Issues an HSR %11 to each channel to initialize the function.
7. Enables servicing by assigning H, M, or L priority to the channel priority bits. Both QDEC chan-nels
must be assigned the same priority to ensure correct operation.
The TPU then executes the initialization state and starts decoding the two input signals. When initial-ization
is complete, the HSR bit values for both channels are %00.
NOTE:
CHAN_PINSTATE parameters must not be read by the CPU until after the TPU
has negated the HSR bits during initialization.
7 Performance and Use of Function
NOTE: Execution times do not include the time slot transition time (TST = 10 or 14 CPU clocks)
Since the scheduler assures that worst-case latencies in any TPU application can be closely estimated,
7.1 Performance
Like all TPU functions, the performance limit of the QDEC function in a given application is dependent
upon the service time (latency) of other active TPU channels. This is due to the operational nature of
the scheduler. When a pair of QDEC channels are being used and no other TPU channels are active,
the minimum time between count edges on the two channels is 42 CPU clock cycles. This is equivalent
to a count rate of approximately 400,000 counts per second with a system clock speed of 16.78 MHz,
or a count rate of approximately 500,000 counts per second with a system clock speed of 20.97 MHz.
When more TPU channels are active, performance is lessened; if two sets of encoder signals are
decoded using four channels, then the maximum count rate with a 16.78-kHz bus is limited to approxi-mately
200,000 counts. Use of other functions, such as PWM, also lessens performance.
it is recommended that the guidelines in the TPU Reference Manual (TPURM/ AD) be used with the fig-ures
given in the quadrature decode function state timing table to perform an analysis of any proposed
application that appears to approach the performance limits of the TPU. If the QDEC function fails to
meet the system performance requirements, then fast quadrature decode (FQD) TPU function should
be evaluated as an alternative.
| State Number | Name | Max. CPU Clock Cycles | RAM Accesses by TPU |
| S1 | INIT_QDEC | 12 | 3 |
| S2 | READ_TCR1_QDEC | 2 | 1 |
| S3 | EDGE_QDEC | 28 | 8 |
7.3 Noise Immunity
Despite these precautions, there may be situations where noise on both channels simultaneously caus-es
The following examples are intended to illustrate the extent of the noise immunity inherent in the TPU
CASE A: Short positive or negative pulses two CPU clocks or less in duration.
CASE B: Positive or negative pulses four CPU clocks or greater in duration, but less than TPU
CASE C: Positive or negative pulses four CPU clocks or greater in duration and greater than TPU
Pulses of three CPU clocks in length may pass through the input filter - they can either be case A or
7.4 Using QDEC with Three-Signal Encoders
Three-signal encoders can be decoded when QDEC is used in conjunction with the TPU function called
7.5 Using the Time Stamp Feature
7.6 EDGE_TIME and POSITION_COUNT Coherency
This problem can be handled by performing multiple CPU reads of the two parameters with a delay be-tween
GET_PARAM: Read EDGE_TIME and POSITION_COUNT
7.7 TCR1 Timebase Read
Since the CPU must issue an HSR to obtain the latest TCR1_VALUE, and since that HSR is subject to
In the best case (TPU idle at time of HSR issue) there is a delay equivalent to 16 CPU clocks between
7.8 Using QDEC as a Discrete Input/ Transition Counter
When the QDEC function is configured as described, CHAN_PINSTATE is updated as each transition
An immediate update of CHAN_PINSTATE can be invoked at any time by issuing an HSR %11. The
8 Function Examples
8.1 Example A
8.1.2 Initialization
POSITION_COUNT = $1000
8.2 Example B
8.2.2 Initialization
TRANS_COUNT (POSITION_COUNT) = $0000
Note that the TCR1 read HSR can still be used when QDEC is operating in this mode.
Table 2 Channel 1 (Primary) Parameter RAM
Table 3 Channel 2 (Secondary) Parameter RAM
Table 4 Channel 12 Parameter RAM
9.1 STATE 1: INIT_QDEC
The channel is configured as an input with TCR1 as a timebase
9.2 STATE 2: READ_TCR1_QDEC
The current value of TCR1 is read and stored in TCR1_VALUE
To a large extent, TPU hardware and the QDEC function microcode protect the counter from erroneous
updates due to noise. All TPU input channels incorporate a digital filter which rejects pulses of less than
two CPU clocks and guarantees to pass pulses of greater than four CPU clocks. In addition, when ser-vicing
a transition in normal mode, the QDEC function always checks the new pin state against the pin
state from the last service, and if they are equal then no action is taken. This protects against a noise
pulse that is long enough to get through the digital filter, but not long enough to last from the actual tran-sition
time to the time that the TPU services the channel.
erroneous updates of the counter. Under these conditions, it is recommended that additional external
protection, such as Schmitt trigger buffers or an additional filter stage, be added.
itself and the QDEC function.
Result: Rejected by hardware filter on TPU input pins - no service requests.
service latency at the time of the pulse.
Result: One service request per pulse - rejected in software by pin state history test.
service latency at the time of the pulse.
Result: Two service requests per pulse. Both edges are serviced and counted resulting in a net error of
zero on POSITION_COUNT.
case B. Noise rejection cannot be guaranteed when case C noise exists simultaneously on both chan-nels.
Many shaft encoders supply two quadrature signals plus an index signal that generates a pulse once
per revolution. This pulse usually has a fixed relationship to other system parameters and is used for
alignment during startup.
new input transition counter (NITC). QDEC decodes the quadrature signals and the index pulse is fed
to the NITC channel. NITC allows any location in parameter RAM to be captured on a specified edge
and the value presented to the CPU. In this case, NITC would be configured to capture the
POSITION_COUNT parameter of QDEC. The NITC channel should be run on a lower channel number
than the QDEC primary channel, and assigned the same priority as the QDEC channel.
The time stamp feature has been provided to allow the CPU to perform speed and position interpolation
at very slow encoder speeds. At low speeds, the number of transitions counted between CPU reads of
POSITION_COUNT is too small to provide reliable information. Due to the following restrictions, the
time stamp feature should be used with care.
The TPU cannot coherently update both the EDGE_TIME and POSITION_COUNT parameters during
the service of a transition. A CPU read of these two parameters may return values that do not correlate,
such as a new EDGE_TIME with an 'old' POSITION_COUNT value (EDGE_TIME is updated first).
the reads. The delay must be greater than or equal to the worst-case time between the TPU writ-ing
EDGE_TIME and POSITION_COUNT of ten CPU clocks. For example, the following CPU action
could be used.
LOOP: Store EDGE_TIME in TEMP1 and POSITION_COUNT in TEMP2
Delay 10 CPU clocks
Read EDGE_TIME and POSITION_COUNT
If EDGE_TIME != TEMP1 or POSITION_COUNT != TEMP2 then
goto LOOP
Endif
VALID: TEMP1 and TEMP2 are coherent and valid.
To actually perform interpolation, the CPU must obtain valid EDGE_TIME and POSITION_COUNT pa-rameters
as described above, then read the TCR1 timebase at fixed intervals to calculate a new posi-tion.
normal TPU scheduling, there is an uncertainty in the returned TCR1_VALUE that is dependent upon
both TPU latency at the time of issuing the HSR and upon the selected prescaler value for TCR1.
the time the CPU writes the HSR bits and the time the TPU writes TCR1_VALUE and clears the HSR
bits.
A single TPU channel programmed to run QDEC can be used as a discrete input pin and transition
counter. To be used in this way, the channel must be programmed as a primary channel. The
EDGE_TIME_LSB_ADDR parameter must point to the LSB of the channel's own parameter 0 and the
CORR_PINSTATE_ADDR parameter must point to the channel's own CHAN_PINSTATE parameter.
An HSR %11 should be issued to initialize the function.
is serviced, and contains a value representing the latest pin level ($ 8000 = high, $0000 = low).
POSITION_COUNT holds the number of transitions on the pin (positive and negative).
CPU should not interpret the value of CHAN_PINSTATE until the TPU has completed the host service
request and the HSR bits have been negated.
The following examples show configuration of the quadrature decode function for both quadrature de-code
and for operation as an input pin with transition counter. Each example includes a description of
the example, a diagram of the initial parameter RAM content, and the initial control bit settings.
8.1.1 Description
Configure channels 1 and 2 to run QDEC. The initial position should be $1000.
Disable channels 1 and 2 by clearing priority bits (CPR1[ 3: 2] and CPR1[ 5: 4]). Select QDEC function by
programming the function select register of each channel. Configure parameter RAM of each channel
as shown below. Write HSQR1[ 3: 2] = %00 (channel 1 primary) and HSQR1[ 5: 4] = %01 (channel 2 sec-ondary).
Write HSRR1[ 3: 2] and HSRR1[ 5: 4] = %11 to initialize both channels and start quadrature de-code.
Write the priority bits of both channels to the same non-zero value.
The function now runs, decodes transitions on channel 1 or 2, and increments or decrements
POSITION_COUNT accordingly. The CPU can read or write POSITION_COUNT at any time.
8.2.1 Description
Configure channel 12 to act as an input pin with a transition counter. Initialize the counter to zero.
Disable channel 12 by clearing priority bits (CPR0[ 9: 8]). Select QDEC function by programming the
function select register of channel 12. Configure channel 12 parameter RAM as shown below. Write
HSQR0[ 9: 8] = %00 (primary channel). Write HSRR0[ 9: 8] = %11 to channel 12 to initialize, read pin level
and start counting transitions. Write channel 12 priority bits to a non-zero value.
The function now runs, detects transitions on channel 12, and increments the transition counter
(POSITION_COUNT) accordingly. On completion of the initialization HSR and any subsequent edge
service, the parameter CHAN_PINSTATE contains the latest level of the channel pin ($ 8000 for high,
$0000 for low). The CPU can read or write the transition counter at any time.
15 8 0
$YFFF10 x x x x x x x x x x x x x x x x EDGE_TIME
$YFFF12 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 POSITION_COUNT
$YFFF14 x x x x x x x x x x x x x x x x TCR1_VALUE
$YFFF16 x x x x x x x x x x x x x x x x CHAN_PINSTATE
$YFFF18 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 $26
$YFFF1A 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 $11
15 8 0
$YFFF20 x x x x x x x x x x x x x x x x
$YFFF22 x x x x x x x x x x x x x x x x
$YFFF24 x x x x x x x x x x x x x x x x TCR1_VALUE
$YFFF26 x x x x x x x x x x x x x x x x CHAN_PINSTATE
$YFFF28 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 $16
$YFFF2A 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 $11
15 8 0
$YFFFC0 x x x x x x x x x x x x x x x x EDGE_TIME
$YFFFC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANS_COUNT
$YFFFC4 x x x x x x x x x x x x x x x x TCR1_VALUE
$YFFFC6 x x x x x x x x x x x x x x x x CHAN_PINSTATE
$YFFFC8 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 $C6
$YFFFCA 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 $C1
9 Function Algorithm
The quadrature decode function consists of three states, which operate as described below. The follow-ing
description is provided as a guide only, to aid understanding of the function. The exact sequence of
operations in microcode may be different to optimize speed and code size. TPU microcode source list-ings
for all functions in the TPU function library can be downloaded from the Motorola Freeware bulletin
board. Refer to Using the TPU Function Library and TPU Emulation Mode (TPUPN00/ D) for detailed
instructions on downloading and compiling microcode.
This state is entered as a result of a host service request type %11.
The pin is configured to detect any transition
Transition service requests are enabled
The current pin state is read
If the pin is low
$0000 is stored in CHAN_PINSTATE
Else
$8000 is stored in CHAN_PINSTATE
Endif
The current value of TCR1 is read and stored in TCR1_VALUE
The state ends
This state is entered as a result of a host service request type %10.
The state ends
| Serviced Transition | Test Description |
| Primary Rising | If last secondary transition was falling, then primary channel is leading secondary channel and POSITION_COUNT is incremented.
If last secondary transition was rising, then primary channel is lagging secondary channel and POSITION_COUNT is decremented. |
| Primary Falling | If last secondary transition was rising, then primary channel is leading secondary channel and POSITION_COUNT is incremented.
If last secondary transition was falling, then primary channel is lagging secondary channel and POSITION_COUNT is decremented. |
| Secondary Rising | If last primary transition was rising, then primary channel is leading secondary channel and POSITION_COUNT is incremented.
If last primary transition was falling, then primary channel is lagging secondary channel and POSITION_COUNT is decremented. |
| Secondary Falling | If last primary transition was falling, then primary channel is leading secondary channel and POSITION_COUNT is incremented.
If last primary transition was rising, then primary channel is lagging secondary channel and POSITION_COUNT is decremented. |