(**********************************************************************) (* *) (* Function: SPWM - Synchronised Pulse Width Modulation *) (* *) (* Creation Date: Pre 89 From: NEW *) (* *) (* Author: Motorola *) (* *) (* Description: *) (* ------------ *) (* Generate pulse width modulated waveform, with a phase relationship *) (* to another (SPWM?) channel. 3 distinct modes of operation. *) (* 0% and 100% duty cycles not supported - use standard pwm function. *) (* *) (* Updates: By: Modification: *) (* -------- --- ------------- *) (* 28/Feb/92 JW Cleaned up for inclusion in Library *) (* 11/Apr/93 JL Converted to new syntax. *) (* *) (*--------------------------------------------------------------------*) (* Standard Exits Used:- End_Of_Phase: Y End_Of_Link: N *) (* *) (* External Files %included: LINKCHAN. *) (* *) (* CODE SIZE excluding standard exits = 54 LONG WORDS *) (*--------------------------------------------------------------------*) (* *) (* *) (********** This Revision: 2.0 *********) (* *) (* Functionally identical to 68332 TPU ROM of masks D33F, D87M, 2D87M *) (* *) (********** LAST MODIFIED: 11/Apr/93 BY: Jeff Loeliger ********) (* *) (**********************************************************************) (***************************************************************************) (*Motorola reserves the right to make changes without further notice to any*) (*product herein. Motorola makes no warranty, representation or guarantee *) (*regarding the suitability of its products for any particular purpose, nor*) (*does Motorola assume any liability arising out of the application or use *) (*of any product or circuit, and specifically disclaims any and all *) (*liability, including without limitation consequential or incidental *) (*damages. "Typical" parameters can and do vary in different applications. *) (*All operating parameters, including "Typical",must be validated for each *) (*customer application by customer's technical experts. Motorola does not *) (*convey any license under its patent rights nor the rights of others. *) (*Motorola products are not designed, intended, or authorized for use as *) (*components in systems intended for surgical implant into the body, or *) (*other applications intended to support or sustain life, or for any other *) (*application in which the failure of the Motorola product could create a *) (*situation where injury or death may occur. Should Buyer purchase or use *) (*Motorola products for any such unintended or unauthorized application, *) (*Buyer, shall indemnify and hold Motorola and its officers, employees, *) (*subsidiaries, affiliates, and distributors harmless against all claims, *) (*costs, damages, and expenses, and reasonable attorney fees arising out *) (*of, directly or indirectly, any claim of personal injury or death *) (*associated with such unintended or unauthorized use, even if such claim *) (*alleges that Motorola was negligent regarding the design or manufacture *) (*of the part. *) (*Motorola and the Motorola logo are registered trademarks of Motorola Inc.*) (*Motorola is an Equal Opportunity/Affirmative Action Employer. *) (*Copyright Motorola Inc. 1993 *) (***************************************************************************) (* Parameters *) %macro CHANNEL_CONTROL_SPWM 'prm0'. %macro LASTRISE 'prm0'. %macro NEXTRISE 'prm1'. %macro HIGHTIME 'prm2'. %macro PERIOD 'prm3'. %macro DELAY_MD01 'prm3'. %macro REF_ADDRS 'prm4'. %macro LINK_CONTROL 'prm4'. %macro DELAY_MDX0 'prm5'. %macro REF_VALUE 'prm5'. %macro CHAN_CONT_REG_SP 'p_low'. %include 'linkchan.UC'. (* include subroutine to link to a block of channels. *) (**********************************************************************) (* *) (* STATE : Init_spwm *) (* *) (* PRELOAD PARAMETER : CHANNEL CONTROL *) (* *) (* ENTER WHEN : HSR 11 is issued *) (* *) (* ACTION : *) (* 1.LASTRISE gets the value of the matched tcr *) (* 2.Match is generated according to mode *) (* *) (**********************************************************************) %entry start_address *; ram p<-@CHANNEL_CONTROL_SPWM; disable_match; name = Init_spwm; cond hsr1=1,hsr0=0. Init_spwm : au nil :=<< @CHAN_CONT_REG_SP, ccl; chan clear flag0. chan config := p, enable_mtsr; if N = 0 then goto Mode_test; chan clear flag1. (* Get tcr1 *) au ert := tcr1; chan neg_tdl, neg_mrl. (* Get tcr2 *) au ert := tcr2. Mode_test : if hsq0 = 0 then goto Trans_L_H_MDX0. ram p <- @PERIOD. (* get period if hsq0 = 0 *) ram p <- @REF_ADDRS; (*or ref_addrs if hsq0 = 1*) chan set flag0. (* phase Trans_L_H_MD01 is executed next *) (**********************************************************************) (* *) (* STATE : Trans_L_H_MD01 *) (* *) (* PRELOAD PARAMETER : REF_ADDRS *) (* *) (* ENTER WHEN : low to high transition occured in mode 1 *) (* *) (* ACTION : *) (* 1.current time is stored in lastrise *) (* 2.high_low match is generated on ert + hightime + *) (* delay *) (* 3.update nextrise *) (* 4.ref_value updated *) (* 5.Interrupt request is asserted *) (* *) (**********************************************************************) %entry start_address *; ram p<-@REF_ADDRS; name = Trans_L_H_MD01; cond hsr1=0,hsr0=0,m/tsr=1,pin=1,flag0=1. Trans_L_H_MD01 : au diob := ert; ram diob -> @LASTRISE. (* diob = adr1 *) au diob := p. (* diob = adr2 ; p <- (adr1) *) au diob := p_high; ram p <- by_diob. au a := p; ram diob <- by_diob. ram diob -> @REF_VALUE. (* sr = (adr2) ; p <- hightime *) au sr := diob; ram p <- @HIGHTIME. (* a = (adr1) + hightime ; p <- delay *) au a := a + p; ram p <- @DELAY_MD01. (* ert = (adr1) + hightime + delay *) au ert := a + p; chan write_mer, neg_mrl, neg_lsl, pac := high_low; chan set flag0; chan cir. (* diob = (adr2) + delay ; diob -> nextrise *) au diob := sr + p; ram diob -> @NEXTRISE; end. (**********************************************************************) (* *) (* STATE : Trans_H_L_MD01 *) (* *) (* PRELOAD PARAMETER : NEXTRISE *) (* *) (* ENTER WHEN : A falling transition has occurred *) (* *) (* ACTION : *) (* NEXTRISE written to ert *) (* *) (**********************************************************************) %entry start_address Setup_next_rise; ram diob<-@NEXTRISE; name = Trans_H_L_MD01; cond hsr1=0,hsr0=0,m/tsr=1,pin=0,lsr=0,flag0=1. (**********************************************************************) (* *) (* STATE : Immed_Link_MD01 *) (* *) (* PRELOAD PARAMETER : DELAY *) (* *) (* ENTER WHEN : HSR10 or link is issued *) (* *) (* ACTION : *) (* 1.If MDX0, do nothing *) (* 2.Otherwise, calculate new NEXTRISE *) (* 3.If pin = 0, chan set new rise time *) (* *) (**********************************************************************) %entry start_address *; ram p<-@DELAY_MD01; disable_match; name = Immed_link_MD01; cond hsr1=1,hsr0=1. if flag0 = 0 then goto End_of_phase, flush. (**********************************************************************) %entry start_address *; ram p<-@DELAY_MD01; disable_match; name = Immed_link_MD01; cond hsr1=0,hsr0=0,m/tsr=0,lsr=1,flag0=1. (**********************************************************************) %entry start_address *; ram p<-@DELAY_MD01; disable_match; name = Immed_link_MD01; cond hsr1=0,hsr0=0,m/tsr=1,pin=0,lsr=1,flag0=1. (**********************************************************************) ram diob <- @REF_VALUE; chan neg_lsl. if PSL = 1 then goto End_of_phase. au p := diob + p; ram p -> @NEXTRISE. au ert := p; chan write_mer, neg_mrl,pac := low_high; chan clear flag1; end. (**********************************************************************) (* *) (* STATE : Trans_L_H_LINK_MDX0 *) (* *) (* PRELOAD PARAMETER : REF_ADDRS *) (* *) (* ENTER WHEN : low to high transition and link occurred in mode 1. *) (* *) (* ACTION : *) (* sum of reference time and delay is stored into *) (* ert and phase trans_l_h_mdx0 is executed. *) (* *) (**********************************************************************) %entry start_address *; ram p<-@PERIOD; name = TR_L_H_LK_MDX0; cond hsr1=0,hsr0=0,m/tsr=1,lsr=1,pin=1,flag0=0. Trans_L_H_LINK_MDX0 : chan neg_lsl; chan set flag1. (**********************************************************************) (* *) (* STATE : Trans_L_H_MDX0 *) (* *) (* PRELOAD PARAMETER : PERIOD *) (* *) (* ENTER WHEN : low to high transition occured in mode 0 or 2 *) (* *) (* ACTION : *) (* 1.current time is stored is LASTRISE *) (* 2.high_low match is generated on ert + hightime *) (* 3.update nextrise *) (* 4.Interrupt request is asserted *) (* *) (**********************************************************************) %entry start_address *; ram p<-@PERIOD; name = Trans_L_H_MDX0; cond hsr1=0,hsr0=0,m/tsr=1,lsr=0,pin=1,flag0=0. Trans_L_H_MDX0 : au diob := ert; ram diob -> @LASTRISE. (* diob = period + lastime : p <- hightime *) au diob := p + diob; ram p <- @HIGHTIME. (* ert = ert + hightime *) au ert := ert + p; chan write_mer, neg_mrl, pac := high_low; chan clear flag0; chan cir. (* mode 0 or 2? *) if hsq1 = 0 then goto Update_nextrise, flush. ram p <- @LINK_CONTROL. au dec := p_high. (* prapare dec for link *) call Link_chan, flush; dec_return. Update_nextrise : ram diob -> @NEXTRISE; end. (**********************************************************************) (* *) (* STATE : LINK1_MDX0 *) (* *) (* PRELOAD PARAMETER : REF_ADDRS *) (* *) (* ENTER WHEN : a link has occurred in mode 0. A match causing a *) (* H-L transition may or may not have occurred. *) (* ACTION : *) (* sum of reference time, delay, and period is stored *) (* into ert. *) (* *) (**********************************************************************) %entry start_address *; ram p<-@REF_ADDRS; name = LINK1_MDX0; cond hsr1=0,hsr0=0,m/tsr=0,lsr=1,flag0=0. chan neg_lsl; chan set flag1; end. (**********************************************************************) (* *) (* STATE : Trans_H_L_MDX0 *) (* *) (* PRELOAD PARAMETER : NEXTRISE *) (* *) (* ENTER WHEN : A falling transition has occurred *) (* *) (* ACTION : *) (* NEXTRISE written to ert *) (* *) (**********************************************************************) %entry start_address *; ram diob<-@NEXTRISE; name = Trans_H_L_MDX0; cond hsr1=0,hsr0=0,m/tsr=1,lsr=0,pin=0,flag0=0. if flag1 = 0 then goto Setup_next_rise, flush. ram p <- @REF_ADDRS. (**********************************************************************) (* *) (* STATE : LINK2_MDX0 *) (* *) (* PRELOAD PARAMETER : REF_ADDRS *) (* *) (* ENTER WHEN : a link has occurred in mode 0 while pin is high *) (* *) (* ACTION : *) (* sum of reference time, delay, and period is stored *) (* into ert. *) (* *) (**********************************************************************) %entry start_address *; ram p<-@REF_ADDRS; name = LINK2_MDX0; cond hsr1=0,hsr0=0,m/tsr=1,lsr=1,pin=0,flag0=0. au diob := p_low; ram p <- @DELAY_MDX0. (* get the parameter pointed to by the lower byte of ref_addr *) ram diob <- by_diob; chan neg_lsl. (* save the sum of reference time and delay *) au diob := diob + p; ram p <- @PERIOD. au diob := diob + p; ram diob -> @NEXTRISE. Setup_next_rise : au ert := diob; chan write_mer, neg_mrl,pac := low_high; chan clear flag1; end. (**********************************************************************) (* UNUSED ENTRIES - execute an end *) (**********************************************************************) %entry start_address End_of_phase; name = Spwm_undef; cond hsr1=0,hsr0=1.